Low level hardware interface descriptions and functionality.
More...
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| file | joybus.h |
| | Joybus Subsystem.
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| file | mi.h |
| | MI register definitions.
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| file | regsinternal.h |
| | Register definitions for various hardware in the N64.
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#define | JOYBUS_BLOCK_SIZE 64 |
| | Size of a Joybus input/output block in bytes.
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#define | JOYBUS_BLOCK_DWORDS ( JOYBUS_BLOCK_SIZE / sizeof(uint64_t) ) |
| | Size of a Joybus input/output block in double-words.
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| void | joybus_exec (const void *inblock, void *outblock) |
| | Write a 64-byte block of data to the PIF and read the 64-byte result. More...
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Low level hardware interface descriptions and functionality.
The low level hardware interfaces handle several functions in the N64 that would otherwise be handled by a kernel or RTOS. This includes the DMA Controller, the Exception Handler, the Interrupt Controller and the N64 System Interface. The DMA controller handles DMA requests between the cartridge and the N64 RDRAM. Other systems in the N64 have their own DMA controllers that are handled in the relevant subsystems. The exception handler traps any exceptions raised by the N64, including the reset exception. The interrupt handler sets up the MIPS interface (MI) which handles low level interrupt functionality for all other systems in the N64. The N64 system interface provides the ability for code to manipulate cache and boot options.
◆ AI_regs_t
Register definition for the AI interface.
| Data Fields |
|---|
|
volatile void * |
address |
Pointer to uncached memory buffer of samples to play. |
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uint32_t |
length |
Size in bytes of the buffer to be played. Should be number of stereo samples * 2 * sizeof( uint16_t ) |
|
uint32_t |
control |
DMA start register. Write a 1 to this register to start playing back an audio sample. |
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uint32_t |
status |
AI status register. Bit 31 is the full bit, bit 30 is the busy bit. |
|
uint32_t |
dacrate |
Rate at which the buffer should be played. Use the following formula to calculate the value: ((2 * clockrate / frequency) + 1) / 2 - 1
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|
uint32_t |
bitrate |
Half-rate at which each single bit of a sample is shifted into the DAC. Allowed values are 0..15, with "0" turning off the audio output. Values 1 and 2 are a valid hardware configuration for the DAC, but result in audio corruption because AI isn't able to shift bits that fast.
The maximum value that still allows samples to play correctly is dacrate / 66 (consider this is a half-rate and there are 2 16-bit samples). Lower values will work too, though.
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◆ VI_regs_t
Register definition for the VI interface.
| Data Fields |
|---|
|
uint32_t |
control |
VI control register. Sets up various rasterization modes. |
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void * |
framebuffer |
Pointer to uncached buffer in memory to rasterize. |
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uint32_t |
width |
Width of the buffer in pixels. |
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uint32_t |
v_int |
Vertical interrupt control register. Controls which horizontal line must be hit to generate a VI interrupt. |
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uint32_t |
cur_line |
Current vertical line counter. |
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uint32_t |
timing |
Timing generation register for PAL/NTSC signals. |
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uint32_t |
v_sync |
Number of lines per frame. |
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uint32_t |
h_sync |
Number of pixels in line and leap pattern. |
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uint32_t |
h_sync2 |
Number of pixels in line, set identically to h_sync. |
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uint32_t |
h_limits |
Beginning and end of video horizontally. |
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uint32_t |
v_limits |
Beginning and end of video vertically. |
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uint32_t |
color_burst |
Beginning and end of color burst in vertical lines. |
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uint32_t |
h_scale |
Horizontal scaling factor from buffer to screen. |
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uint32_t |
v_scale |
Vertical scaling factor from buffer to screen. |
◆ PI_regs_t
Register definition for the PI interface.
| Data Fields |
|---|
|
volatile void * |
ram_address |
Uncached address in RAM where data should be found. |
|
uint32_t |
pi_address |
Address of data on peripheral. |
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uint32_t |
read_length |
How much data to read from RAM into the peripheral. |
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uint32_t |
write_length |
How much data to write to RAM from the peripheral. |
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uint32_t |
status |
Status of the PI, including DMA busy. |
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uint32_t |
dom1_latency |
Cartridge domain 1 latency in RCP clock cycles. Requires DMA status bit guards to work reliably. |
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uint32_t |
dom1_pulse_width |
Cartridge domain 1 pulse width in RCP clock cycles. Requires DMA status bit guards to work reliably. |
◆ SI_regs_t
Register definition for the SI interface.
| Data Fields |
|---|
|
volatile void * |
DRAM_addr |
Uncached address in RAM where data should be found. |
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volatile void * |
PIF_addr_read |
Address to read when copying from PIF RAM. |
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uint32_t |
reserved1 |
Reserved word. |
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uint32_t |
reserved2 |
Reserved word. |
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volatile void * |
PIF_addr_write |
Address to write when copying to PIF RAM. |
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uint32_t |
reserved3 |
Reserved word. |
|
uint32_t |
status |
SI status, including DMA busy and IO busy. |
◆ SP_regs_t
Register definition for the SP interface.
| Data Fields |
|---|
|
volatile void * |
RSP_addr |
RSP memory address (IMEM/DMEM) |
|
volatile void * |
DRAM_addr |
RDRAM memory address. |
|
uint32_t |
rsp_read_length |
RDRAM->RSP DMA length. |
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uint32_t |
rsp_write_length |
RDP->RDRAM DMA length. |
|
uint32_t |
status |
RSP status. |
|
uint32_t |
rsp_dma_full |
RSP DMA full. |
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uint32_t |
rsp_dma_busy |
RSP DMA busy. |
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uint32_t |
rsp_semaphore |
RSP Semaphore. |
◆ joybus_exec()
| void joybus_exec |
( |
const void * |
input, |
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|
void * |
output |
|
) |
| |
Write a 64-byte block of data to the PIF and read the 64-byte result.
This function is not a stable feature of the libdragon API and should be considered experimental!
The usage of this function will likely change as a result of the ongoing effort to integrate the multitasking kernel with asynchronous operations.
- Parameters
-
| [in] | input | Source buffer for the input block to send to the PIF |
| [out] | output | Destination buffer to place the output block from the PIF |
