libdragon
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Video Interface Subsystem. More...
Go to the source code of this file.
Data Structures | |
struct | vi_config_t |
Video Interface register structure. More... | |
Macros | |
#define | VI_REGISTERS_ADDR 0xA4400000 |
Register uncached location in memory of VI. | |
#define | VI_REGISTERS_COUNT 14 |
Number of useful 32-bit registers at the register base. | |
#define | VI_REGISTERS ((volatile uint32_t*)VI_REGISTERS_ADDR) |
Base pointer to hardware Video interface registers that control various aspects of VI configuration. Shouldn't be used by itself, use VI_ registers to get/set their values. | |
#define | VI_CTRL (&VI_REGISTERS[0]) |
VI Index register of controlling general display filters/bitdepth configuration. | |
#define | VI_ORIGIN (&VI_REGISTERS[1]) |
VI Index register of RDRAM base address of the video output Frame Buffer. This can be changed as needed to implement double or triple buffering. | |
#define | VI_WIDTH (&VI_REGISTERS[2]) |
VI Index register of width in pixels of the frame buffer. | |
#define | VI_V_INTR (&VI_REGISTERS[3]) |
VI Index register of vertical interrupt. | |
#define | VI_V_CURRENT (&VI_REGISTERS[4]) |
VI Index register of the current half line, sampled once per line. | |
#define | VI_BURST (&VI_REGISTERS[5]) |
VI Index register of sync/burst values. | |
#define | VI_V_SYNC (&VI_REGISTERS[6]) |
VI Index register of total visible and non-visible lines. This should match either NTSC (non-interlaced: 0x20D, interlaced: 0x20C) or PAL (non-interlaced: 0x271, interlaced: 0x270) | |
#define | VI_H_SYNC (&VI_REGISTERS[7]) |
VI Index register of total width of a line. | |
#define | VI_H_SYNC_LEAP (&VI_REGISTERS[8]) |
VI Index register of an alternate scanline length for one scanline during vsync. | |
#define | VI_H_VIDEO (&VI_REGISTERS[9]) |
VI Index register of start/end of the active video image, in screen pixels. | |
#define | VI_V_VIDEO (&VI_REGISTERS[10]) |
VI Index register of start/end of the active video image, in screen half-lines. | |
#define | VI_V_BURST (&VI_REGISTERS[11]) |
VI Index register of start/end of the color burst enable, in half-lines. | |
#define | VI_X_SCALE (&VI_REGISTERS[12]) |
VI Index register of horizontal subpixel offset and 1/horizontal scale up factor. | |
#define | VI_Y_SCALE (&VI_REGISTERS[13]) |
VI Index register of vertical subpixel offset and 1/vertical scale up factor. | |
#define | VI_TO_REGISTER(index) (((index) >= 0 && (index) <= VI_REGISTERS_COUNT)? &VI_REGISTERS[index] : NULL) |
VI register by index (0-13) | |
#define | VI_TO_INDEX(reg) ((reg) - VI_REGISTERS) |
VI index from register. | |
#define | VI_DEDITHER_FILTER_ENABLE (1<<16) |
VI_CTRL Register setting: enable dedither filter. | |
#define | VI_PIXEL_ADVANCE_DEFAULT (0b0011 << 12) |
VI_CTRL Register setting: default value for pixel advance. | |
#define | VI_PIXEL_ADVANCE_BBPLAYER (0b0001 << 12) |
VI_CTRL Register setting: default value for pixel advance on iQue. | |
#define | VI_AA_MODE_NONE (0b11 << 8) |
VI_CTRL Register setting: disable AA / resamp. | |
#define | VI_AA_MODE_RESAMPLE (0b10 << 8) |
VI_CTRL Register setting: disable AA / enable resamp. | |
#define | VI_AA_MODE_RESAMPLE_FETCH_NEEDED (0b01 << 8) |
VI_CTRL Register setting: enable AA / enable resamp, fetch pixels when needed. | |
#define | VI_AA_MODE_RESAMPLE_FETCH_ALWAYS (0b00 << 8) |
VI_CTRL Register setting: enable AA / enable resamp, fetch pixels always. | |
#define | VI_CTRL_SERRATE (1<<6) |
VI_CTRL Register setting: enable interlaced output. | |
#define | VI_DIVOT_ENABLE (1<<4) |
VI_CTRL Register setting: enable divot filter (fixes 1 pixel holes after AA). | |
#define | VI_GAMMA_ENABLE (1<<3) |
VI_CTRL Register setting: enable gamma correction filter. | |
#define | VI_GAMMA_DITHER_ENABLE (1<<2) |
VI_CTRL Register setting: enable gamma correction filter and hardware dither the least significant color bit on output. | |
#define | VI_CTRL_TYPE (0b11) |
VI_CTRL Register setting: framebuffer source format. | |
#define | VI_CTRL_TYPE_32_BPP (0b11) |
VI_CTRL Register setting: set the framebuffer source as 32-bit. | |
#define | VI_CTRL_TYPE_16_BPP (0b10) |
VI_CTRL Register setting: set the framebuffer source as 16-bit (5-5-5-3). | |
#define | VI_CTRL_TYPE_BLANK (0b00) |
VI_CTRL Register setting: set the framebuffer source as blank (no data and no sync, TV screens will either show static or nothing). | |
#define | VI_ORIGIN_SET(value) ((value & 0xFFFFFF) << 0) |
VI_ORIGIN Register: set the address of a framebuffer. | |
#define | VI_WIDTH_SET(value) ((value & 0xFFF) << 0) |
VI_ORIGIN Register: set the width of a framebuffer. | |
#define | VI_V_CURRENT_VBLANK 2 |
VI_V_CURRENT Register: default value for vblank begin line. | |
#define | VI_V_INTR_SET(value) ((value & 0x3FF) << 0) |
VI_V_INTR Register: set value for vertical interrupt. | |
#define | VI_V_INTR_DEFAULT 0x3FF |
VI_V_INTR Register: default value for vertical interrupt. | |
#define | VI_BURST_START(value) ((value & 0x3F) << 20) |
VI_BURST Register: set start of color burst in pixels from hsync. | |
#define | VI_VSYNC_WIDTH(value) ((value & 0x7) << 16) |
VI_BURST Register: set vertical sync width in half lines. | |
#define | VI_BURST_WIDTH(value) ((value & 0xFF) << 8) |
VI_BURST Register: set color burst width in pixels. | |
#define | VI_HSYNC_WIDTH(value) ((value & 0xFF) << 0) |
VI_BURST Register: set horizontal sync width in pixels. | |
#define | VI_BURST_START_NTSC 62 |
VI_BURST Register: NTSC default start of color burst in pixels from hsync. | |
#define | VI_VSYNC_WIDTH_NTSC 5 |
VI_BURST Register: NTSC default vertical sync width in half lines. | |
#define | VI_BURST_WIDTH_NTSC 34 |
VI_BURST Register: NTSC default color burst width in pixels. | |
#define | VI_HSYNC_WIDTH_NTSC 57 |
VI_BURST Register: NTSC default horizontal sync width in pixels. | |
#define | VI_BURST_START_PAL 64 |
VI_BURST Register: PAL default start of color burst in pixels from hsync. | |
#define | VI_VSYNC_WIDTH_PAL 4 |
VI_BURST Register: PAL default vertical sync width in half lines. | |
#define | VI_BURST_WIDTH_PAL 35 |
VI_BURST Register: PAL default color burst width in pixels. | |
#define | VI_HSYNC_WIDTH_PAL 58 |
VI_BURST Register: PAL default horizontal sync width in pixels. | |
#define | VI_X_SCALE_SET(value) (( 1024*(value) + 320 ) / 640) |
VI_X_SCALE Register: set 1/horizontal scale up factor (value is converted to 2.10 format) | |
#define | VI_Y_SCALE_SET(value) (( 1024*(value) + 120 ) / 240) |
VI_Y_SCALE Register: set 1/vertical scale up factor (value is converted to 2.10 format) | |
Functions | |
void | vi_write_safe (volatile uint32_t *reg, uint32_t value) |
Write a set of video registers to the VI. | |
void | vi_write_config (const vi_config_t *config) |
Write a set of video registers to the VI. | |
Video Interface Subsystem.